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ltc2383-16 1 238316fa for more information www.linear.com/ltc2383-16 typical application features description 16-bit, 1msps, low power sar adc with serial interface the lt c ? 2383-16 is a low noise, low power, high speed 16- bit successive approximation register (sar) adc. operating from a 2.5v supply, the ltc2383 -16 has a 2.5v fully differential input range. the ltc2383-16 consumes only 13mw and achieves 2lsb inl max, no missing codes at 16-bits and 92db snr. the ltc2383 -16 has a high speed spi-compatible serial interface that supports 1.8v, 2.5v, 3.3v and 5v logic while also featuring a daisy-chain mode. the fast 1msps throughput with no cycle latency makes the ltc2383-16 ideally suited for a wide variety of high speed applica tions. an internal oscillator sets the conversion time, easing exter - nal timing considerations. the ltc2383 -16 automatically powers down between conversions, lead ing to reduced power dissipation that scales with the sampling rate. 32k point fft f s = 1msps, f in = 20khz applications n 1msps throughput rate n 2lsb inl (max) n guaranteed 16-bit no missing codes n low power: 13mw at 1msps, 13w at 1ksps n 92db snr (typ) at f in = 20khz n guaranteed operation to 125c n 2.5v supply n fully differential input range 2.5v n external 2.5v reference input n no pipeline delay, no cycle latency n 1.8v to 5v i/o voltages n spi-compatible serial i/o with daisy-chain mode n internal conversion clock n 16-pin msop and 4mm 3mm dfn packages n medical imaging n high speed data acquisition n portable or compact instrumentation n industrial process control n low power battery-operated instrumentation n ate l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. frequency (khz) 0 100 200 300 400 500 C180 amplitude (dbfs) C60 C40 C20C80 C100C120 C140 C160 0 238316 ta02 snr = 92.2dbthd = C106.2db sinad = 92db sfdr = 110.4db lt6350 analog input 0v to 2.5v single-ended- to-differential driver 50 100 100 50 3300pf 10f 0.1f 2.5v ref gnd 1.8v to 5v sample clock chain rdl/sdi sdo sck busy cnv ltc2383-16 in + v dd ov dd in C 2.5v 47f(x5r, 0805 size) 23816 ta01 ltc238x-16 sar adc family part number resolution speed power ltc2383-16 16 1msps 13mw ltc2382-16 16 500ksps 6.5mw ltc2381-16 16 250ksps 3.25mw downloaded from: http:///
ltc2383-16 2 238316fa for more information www.linear.com/ltc2383-16 pin configuration absolute maximum ratings supply voltage (v dd ) ............................................... 2.8v supply voltage (ov dd ) ................................................ 6v reference input (ref) .............................................. 2.8v analog input voltage (note 3) in + , in C ......................... (gnd C 0.3v ) to (ref + 0.3v ) digital input voltage (note 3) ........................... (gnd C 0.3v ) to (ov dd + 0.3v ) (notes 1, 2) 1615 14 13 12 11 10 9 17 gnd 12 3 4 5 6 7 8 gndov dd sdosck rdl/sdi busy gnd cnv chain v dd gnd in + in C gnd refref top view de package 16-lead (4mm 3mm) plastic dfn t jmax = 150c, ja = 43c/w exposed pad (pin 17) is gnd, must be soldered to pcb 12 3 4 5 6 7 8 chain v dd gnd in + in C gnd refref 1615 14 13 12 11 10 9 gndov dd sdosck rdl/sdi busy gnd cnv top view ms package 16-lead (4mm 5mm) plastic msop t jmax = 150c, ja = 110c/w order information lead free finish tape and reel part marking package description temperature range ltc2383cms-16#pbf ltc2383cms-16#trpbf 238316 16-lead plastic msop 0c to 70c ltc2383ims-16#pbf ltc2383ims-16#trpbf 238316 16-lead plastic msop C40c to 85c ltc2383hms-16#pbf ltc2383hms-16#trpbf 238316 16-lead plastic msop C40c to 125c ltc2383cde-16#pbf ltc2383cde-16#trpbf 23836 16-lead (4mm 3mm) plastic dfn 0c to 70c ltc2383ide-16#pbf ltc2383ide-16#trpbf 23836 16-lead (4mm 3mm) plastic dfn C40c to 85c consult ltc marketing for parts specified with wider operating temperature ranges. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ . some packages are available in 500 unit reels through designated sales channels with #trmpbf suffix. digital output voltage (note 3) ........................... (gnd C 0.3v ) to (ov dd + 0.3v ) power dissipation .............................................. 500mw operating temperature range lt c2383 c ................................................ 0c to 70 c lt c2383 i ............................................. C 40 c to 85 c lt c2383 h .......................................... C 40 c to 125 c storage temperature range .................. C 65 c to 150 c http://www.linear.com/product/ltc2383-16#orderinfo downloaded from: http:///
ltc2383-16 3 238316fa for more information www.linear.com/ltc2383-16 dynamic accuracy symbol parameter conditions min typ max units sinad signal-to-(noise + distortion) ratio f in = 20khz l 88.5 92 db snr signal-to-noise ratio f in = 20khz l 89 92 db thd total harmonic distortion f in = 20khz, first 5 harmonics l C106 C99 db sfdr spurious free dynamic range f in = 20khz 108 db C3db input bandwidth 30 mhz aperture delay 2 ns aperture jitter 30 ps transient response full-scale step 250 ns the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and a in = C1dbfs. (notes 4, 8) electrical characteristics symbol parameter conditions min typ max units v in + absolute input range (in + ) (note 5) l C0.05 v ref v v in C absolute input range (in C ) (note 5) l C0.05 v ref v v in + C v in C input differential voltage range v in = v in + C v in C l Cv ref +v ref v v cm common-mode input range l v ref /2C 0.05 v ref /2 v ref /2+ 0.05 v i in analog input leakage current l 1 a c in analog input capacitance sample mode hold mode 45 5 pf pf cmrr input common mode rejection ratio 70 db the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) converter characteristics symbol parameter conditions min typ max units resolution l 16 bits no missing codes l 16 bits transition noise 0.6 lsb rms inl integral linearity error (note 6) l C2 0.8 2 lsb dnl differential linearity error l C1 0.4 1 lsb bze bipolar zero-scale error (note 7) l C6 0.25 6 lsb bipolar zero-scale error drift 3 mlsb/c fse bipolar full-scale error (note 7) l C14 3 14 lsb bipolar full-scale error drift 0.1 ppm/c the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) downloaded from: http:///
ltc2383-16 4 238316fa for more information www.linear.com/ltc2383-16 adc timing characteristics symbol parameter conditions min typ max units f smpl maximum sampling frequency l 1 msps t conv conversion time l 610 730 ns t acq acquisition time t acq = t cyc Ct conv C t busylh (note 10) l 250 ns t cyc time between conversions l 1 us t cnvh cnv high time l 20 ns t busylh cnv to busy delay c l = 20pf (note 11) l 20 ns t cnvl minimum low time for cnv (note 11) l 200 ns t sck sck period (notes 11, 12) l 10 ns t sckh sck high time l 4 ns the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) power requirements symbol parameter conditions min typ max units v dd supply voltage l 2.375 2.5 2.625 v ov dd supply voltage 1.71 5.25 v i dd supply current power down mode power down mode 1msps sample rate conversion done conversion done (h-grade) l l l 5.2 0.5 0.5 6.5 40 110 ma a a p d power dissipation power down mode power down mode 1msps sample rate conversion done conversion done (h-grade) 13 1.25 1.25 16.25 100 275 mw w w the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) reference input symbol parameter conditions min typ max units v ref reference voltage (note 5) l 2.4 2.6 v i ref load current (note 9) l 910 a the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) digital inputs and digital outputs symbol parameter conditions min typ max units v ih high level input voltage l 0.8 ? ov dd v v il low level input voltage l 0.2 ? ov dd v i in digital input current v in = 0v to ov dd l C10 10 a c in digital input capacitance 5 pf v oh high level output voltage i o = C500 a l ov dd C 0.2 v v ol low level output voltage i o = 500 a l 0.2 v i oz hi-z output leakage current v out = 0v to ov dd l C10 10 a i source output source current v out = 0v C10 ma i sink output sink current v out = ov dd 10 ma the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) downloaded from: http:///
ltc2383-16 5 238316fa for more information www.linear.com/ltc2383-16 adc timing characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) symbol parameter conditions min typ max units t sckl sck low time l 4 ns t ssdisck sdi setup time from sck (note 11) l 4 ns t hsdisck sdi hold time from sck (note 11) l 1 ns t sckch sck period in chain mode t sckch = t ssdisck + t dsdo (note 11) l 13.5 ns t dsdo sdo data valid delay from sck c l = 20pf (note 11) l 9.5 ns t hsdo sdo data remains valid delay from sck c l = 20pf (note 10) l 1 ns t dsdobusyl sdo data valid delay from busy c l = 20pf (note 10) l 5 ns t en bus enable time after rdl (note 11) l 16 ns t dis bus relinquish time after rdl (note 11) l 13 ns t ssckrdl sck setup time from rdl/sdi (note 10) l 1 ns t hsckrdl sck hold time from rdl/sdi (note 10) l 16 ns note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may effect device reliability and lifetime. note 2: all voltage values are with respect to ground. note 3: when these pin voltages are taken below ground or above ref or ov dd , they will be clamped by internal diodes. this product can handle input currents up to 100ma below ground or above ref or ov dd without latch-up.note 4: v dd = 2.5v, ov dd = 2.5v, ref = 2.5v, f smpl = 1mhz. note 5: recommended operating conditions. note 6: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 7: bipolar zero-scale error is the offset voltage measured from C0.5lsb when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111. full-scale bipolar error is the worst-case of Cfs or +fs untrimmed deviation from ideal first and last code transitions and includes the effect of offset error. note 8: all specifications in db are referred to a full-scale 2.5v input with a 2.5v reference voltage.note 9: f smpl = 1mhz, i ref varies proportionately with sample rate. note 10: guaranteed by design, not subject to test. note 11: parameter tested and guaranteed at ov dd = 1.71v, ov dd = 2.5v and ov dd = 5.25v. note 12: t sck of 10ns maximum allows a shift clock frequency up to 100mhz for rising capture. 0.8*ov dd 0.2*ov dd 50% 50% 238316f01 0.2*ov dd 0.8*ov dd 0.2*ov dd 0.8*ov dd t delay t width t delay figure 1. voltage levels for timing specifications downloaded from: http:///
ltc2383-16 6 238316fa for more information www.linear.com/ltc2383-16 typical performance characteristics 32k point fft f s = 1msps, f in = 20khz snr, sinad vs input frequency thd, harmonics vs input frequency snr, sinad vs input level, f in = 20khz snr, sinad vs temperature thd, harmonics vs temperature integral nonlinearity vs output code differential nonlinearity vs output code dc histogram output code C2.0 inl error (lsb) 0.0 0.5 1.0 1.5 C0.5C1.0 C1.5 2.0 238316 g01 C32768 C16384 0 16384 32768 frequency (khz) 0 100 200 300 400 500 C180 amplitude (dbfs) C60 C40 C20C80 C100C120 C140 C160 0 238316 g04 snr = 92.2dbthd = C106.2db sinad = 92db sfdr = 110.4db output code C1.0 dnl error (lsb) 0.50.0 C0.5 1.0 238316 g02 C32768 C16384 0 16384 32768 t a = 25c, v dd = 2.5v, ov dd = 2.5v, ref = 2.5v, f smpl = 1msps, unless otherwise noted. input level (db) snr, sinad (dbfs) 93.0 238316 g07 91.0 91.5 92.0 92.5 C40 C30 C20 C10 0 snr sinad temperature (oc) snr, sinad (dbfs) 94.00 238316 g08 91.00 91.50 92.00 92.50 93.00 93.50 C55 C35 C15 5 25 45 65 85 105 125 snr sinad temperature (oc) harmonics, thd (dbfs) C100.00 2383 g09 C120.00 C115.00 C110.00 C105.00 C55 C35 C15 5 25 45 65 85 105 125 thd 2nd 3rd frequency (khz) snr, sinad (dbfs) 93 238316 g05 85 86 87 88 90 9189 92 0 25 50 75 100 125 150 175 200 snr sinad frequency (khz) harmonics, thd (dbfs) C80 238316 g06 C130 C125 C120 C115 C110 C105 C100 C95 C90 C85 0 25 50 75 100 125 150 175 200 thd 3rd 2nd code C2 C1 0 1 2 0 counts 14000001200000 1000000 800000600000 400000 200000 1600000 238316 g03 downloaded from: http:///
ltc2383-16 7 238316fa for more information www.linear.com/ltc2383-16 typical performance characteristics supply current vs temperature shutdown current vs temperature supply current vs sampling rate inl/dnl vs temperature full-scale error vs temperature offset error vs temperature t a = 25c, v dd = 2.5v, ov dd = 2.5v, ref = 2.5v, f smpl = 1msps, unless otherwise noted. sampling rate (khz) 0 200 400 600 800 1000 0 power supply current (ma) 54 2 1 3 6 238316 g15 temperature (c) inl/dnl error (lsb) 1 238316 g10 C1 C0.5 0 0.5 C55 C35 25 45 65 C15 5 85 105 125 max inl max dnl min dnl min inl temperature (c) full-scale error (lsb) 2.5 238316 g11 0 0.5 1.0 1.5 2.0 C55 C35 25 45 65 C15 5 85 105 125 Cfs +fs temperature (c) power supply current (ma) 6 238316 g13 0 1 2 3 4 5 C55 C35 C15 5 25 45 65 85 105 125 i vdd i ref i ovdd temperature (c) offset error (lsb) 0.3 238316 g12 C0.1 0 0.1 0.2 C55 C35 C15 5 25 45 65 85 105 125 temperature (c) power-down current (a) 30 238316 g14 0 5 10 15 20 25 C55 C35 C15 5 25 45 65 85 105 125 i vdd + i ovdd + i ref downloaded from: http:///
ltc2383-16 8 238316fa for more information www.linear.com/ltc2383-16 chain (pin 1) : chain mode selector pin. when low, the ltc2383 -16 operates in normal mode and the rdl/sdi input pin functions to enable or disable sdo. when high, the ltc2383 -16 operates in chain mode and the rdl/ sdi pin functions as sdi, the daisy chain serial data input.v dd (pin 2) : 2.5v digital power supply. the range of v dd is 2.375v to 2.625v . bypass v dd to gnd with a 10f ceramic capacitor. gnd (pins 3, 6, 10 and 16): ground. in + , in C (pins 4, 5) : positive and negative differential analog inputs. ref (pins 7, 8) : reference input. the range of ref is 2.4v to 2.6v . this pin is referred to the gnd pin and should be decoupled closely to the pin with a 47f ceramic capacitor (x5r, 0805 size). cnv (pin 9) : convert input. a rising edge on this input initiates a new conversion. when the conversion is done, the part powers down as long as cnv is held high. when cnv is returned low, the part powers up in preparation for the next conversion. busy (pin 11) : busy indicator. goes high at the start of a new conversion and returns low when the conversion has finished. rdl/sdi (pin 12) : when chain is low, the part is in nor - mal mode and the pin is treated as a bus enabling input. when chain is high, the part is in chain mode and the pin is treated as a serial data input pin where data from another adc in the daisy chain is input. sck (pin 13) : serial data clock input. when sdo is enabled, the conversion result or daisy chain data from another adc is shifted out on the rising edges of this clock msb first. sdo (pin 14) : serial data output. the conversion result or daisy chain data is output on this pin on each rising edge of sck msb first. the output data is in 2 s complement format.ov dd (pin 15) : i/o interface digital power. the range of ov dd is 1.71v to 5.25v . this supply is nominally set to the same supply as the host interface ( 1.8v, 2.5v, 3.3v, or 5v). bypass ov dd to gnd with a 0.1f capacitor. gnd (exposed pad pin 17 C dfn package only) : ground. exposed pad must be soldered directly to the ground plane. functional block diagram pin functions ref = 2.5v ltc2383-16 in + v dd = 2.5v ov dd = 1.8v to 5v in C chaincnv gnd busy sdosck rdl/sdi control logic 16-bit sampling adc spi port +C 238316 bd01 downloaded from: http:///
ltc2383-16 9 238316fa for more information www.linear.com/ltc2383-16 timing diagram power-up acquire power-down convert d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 sdo sck cnv chain, rdl/sdi = 0busy 238316 td02 conversion timing using the serial interface downloaded from: http:///
ltc2383-16 10 238316fa for more information www.linear.com/ltc2383-16 overview the ltc2383 -16 is a low noise, low power, high speed 16-bit successive approximation register (sar) adc. operating from a single 2.5v supply, the ltc2383 -16 supports a large 2.5v fully differential input range, making it ideal for high performance applications which require a wide dynamic range. the ltc2383 -16 achieves 2lsb inl max, no missing codes at 16-bits and 92db snr. fast 1msps throughput with no cycle latency makes the ltc2383 -16 ideally suited for a wide variety of high speed applications. an internal oscillator sets the conversion time, easing external timing considerations. the ltc2383-16 dissipates only 13mw at 1msps , while an auto power-down feature is provided to further reduce power dissipation during inactive periods. converter operation the ltc2383 -16 operates in two phases. during the ac - quisition phase, the charge redistribution capacitor d/a converter (cdac) is connected to the in + and in C pins to sample the differential analog input voltage. a rising edge on the cnv pin initiates a conversion. during the conversion phase, the 16- bit cdac is sequenced through a successive approximation algorithm, effectively comparing the sampled input with binary-weighted fractions of the reference voltage (e.g. v ref /2, v ref /4 v ref /65536) using the differential comparator. at the end of conversion, the cdac output approximates the sampled analog input. the adc control logic then prepares the 16- bit digital output code for serial transfer. transfer function the ltc2383 -16 digitizes the full-scale voltage of 2 ref into 2 16 levels, resulting in an lsb size of 76v with ref = 2.5v . the ideal transfer function is shown in figure 2. the output data is in 2s complement format.analog input the analog inputs of the ltc2383 -16 are fully differential in order to maximize the signal swing that can be digitized. the analog inputs can be modeled by the equivalent circuit applications information figure 2. ltc2383-16 transfer function input voltage (v) 0v output code (two?s complement) ?1 lsb 238316 f02 011...111 011...110000...001 000...000 100...000 100...001 111...110 1 lsb bipolar zero 111...111 fsr/2 ? 1lsb ?fsr/2 fsr = +fs ? ?fs1lsb = fsr/65536 shown in figure 3. the diodes at the input provide esd protection. in the acquisition phase, each input sees ap - proximately 45pf (c in ) from the sampling cdac in series with 40 (r on ) from the on-resistance of the sampling switch. any unwanted signal that is common to both inputs will be reduced by the common mode rejection of the adc. the inputs draw a current spike while charging the c in capacitors during acquisition. during conversion, the analog inputs draw only a small leakage current. r on c in r on ref ref c in in + in C bias voltage 238316 f03 figure 3. the equivalent circuit for the differential analog input of the ltc2383-16 input drive circuits a low impedance source can directly drive the high im - pedance inputs of the ltc2383 -16 without gain error. a high impedance source should be buffered to minimize settling time during acquisition and to optimize the dis - tortion performance of the adc. minimizing settling time downloaded from: http:///
ltc2383-16 11 238316fa for more information www.linear.com/ltc2383-16 applications information is important even for dc inputs, because the adc inputs draw a current spike when entering acquisition. for best performance, a buffer amplifier should be used to drive the analog inputs of the ltc2383 -16. the amplifier provides low output impedance, which produces fast settling of the analog signal during the acquisition phase. it also provides isolation between the signal source and the current spike the adc inputs draw. input filtering the noise and distortion of the buffer amplifier and signal source must be considered since they add to the adc noise and distortion. noisy input signals should be filtered prior to the buffer amplifier input with an appropriate filter to minimize noise. the simple 1- pole rc lowpass filter (l pf1 ) shown in figure 4 is sufficient for many applications. another filter network consisting of l pf2 and the 100 series input resistors should be used between the buffer and adc inputs to both minimize the noise contribution of the buffer and to help minimize disturbances reflected into the buffer from sampling transients. long rc time constants at the analog inputs will slow down the settling of the analog inputs. therefore, l pf2 requires a wider bandwidth than l pf1 . a buffer amplifier with a low noise density must be selected to minimize degradation of the snr. with the 482khz lowpass filter shown in figure 4, the lt6350 provides the full data sheet performance of the ltc2383-16. high quality capacitors and resistors should be used in the rc filters since these components can add distortion. npo and silver mica type dielectric capacitors have excellent linearity. carbon surface mount resistors can generate distortion from self heating and from damage that may occur during soldering. metal film surface mount resistors are much less susceptible to both problems. 50 3300pf 6600pf 50 500 100100 lpf2 lpf1 bw = 482khz bw = 48khz single-ended- to-differential driver single-ended- input signal ltc2383-16 in + in C 238316 f04 lt6350 single-ended-to-differential conversion for single-ended input signals, a single-ended to differential conversion circuit must be used to produce a differential signal at the inputs of the ltc2383 -16. the lt6350 adc driver is recommended for performing single-ended-t o-dif - ferential conversions. the lt6350 is flexible and may be configured to convert single-ended signals of various amplitudes to the 2.5v differential input range of the ltc2383 -16. the lt6350 is also available in h-grade to complement the extended temperature operation of the ltc2383-16 up to 125c. figure 5 shows the lt6350 being used to convert a 0v to 2.5v single-ended input signal. in this case, the first amplifier is configured as a unity gain buffer and the sin - gle-ended input signal directly drives the high-impedance input of the amplifier. as shown in the fft of figure 5a, the lt6350 drives the ltc2383 -16 to full data sheet per - formance without degrading the snr or thd . figure 4. input signal chain lt6350 v cm = v ref /2 2.5v to 0v 0v to 2.5v 0v to 2.5v 238316 f05 out1 r int r int out2 8 4 5 2 1 + C +C C+ frequency (khz) 0 100 200 300 400 500 C180 amplitude (dbfs) C60 C40 C20C80 C100C120 C140 C160 0 238316 f05a snr = 92.2dbthd = C106.2db sinad = 92db sfdr = 110.4db figure 5. lt6350 converting a 0v-2.5v single-ended signal to a 2.5v differential input signal figure 5a. 32k point fft plot for circuit shown in figure 5 downloaded from: http:///
ltc2383-16 12 238316fa for more information www.linear.com/ltc2383-16 the lt6350 can also be used to buffer and convert single-ended signals larger than the input range of the ltc2383 -16 in order to maximize the signal swing that can be digitized. figure 6 shows the lt6350 converting a 0v - 5v single-ended input signal to the 2.5v differential input range of the ltc2383 -16. in this case, the first amplifier in the lt6350 is configured as an inverting amplifier stage, which acts to attenuate the input signal down to the 0v - 2.5v input range of the ltc2383 -16. in the inverting amplifier configuration, the single-ended input signal source no longer directly drives a high impedance input of the first amplifier. the input impedance is instead set by resistor r in . r in must be chosen carefully based on the source impedance of the signal source. higher values of r in tend to degrade both the noise and distortion of the lt6350 and ltc2383-16 as a system. r1, r2 and r3 must be selected in relation to r in to achieve the desired attenuation and to maintain a balanced input impedance in the first amplifier. table 1 applications information lt6350 r1 = 1k r2 = 1kr3 = 2k r4 = 665 v cm = v ref /2 v ref 75pf 150pf 0v to2.5v 2.5v to0v 0v to 5v 238316 f06 out1 r int 10 f r int r in = 2k out2 8 4 5 2 1 + C +C C+ figure 6. lt6350 converting a 0v-5v single-ended signal to a 2.5v differential input signal figure 6a. 32k point fft plot for circuit shown in figure 6 lt6350 r1 = 1.24k r2 = 1.24kr3 = 10k r4 = 1.1k v cm = v ref /2 v cm 0v to2.5v 2.5v to0v 10v 238316 f07 out1 r int r int r in = 10k out2 8 4 5 2 1 + C +C C+ 220pf 10f 200pf shows the resulting snr and thd for several values of r in , r1, r2 and r3 in this configuration. figure 6a shows the resulting fft when using the lt6350 as shown in figure 6. the lt6350 can also be used to buffer and convert large, true bipolar signals which swing below ground to the 2.5v differential input range of the ltc2383 -16. figure 7 shows the lt6350 being used to convert a 10v true bipolar signal for use by the ltc2383 -16. the input im - pedance is again set by resistor r in . table 2 shows the resulting snr and thd for several values of r in . figure 7a shows the resulting fft when using the lt6350 as shown in figure 7. table 1. snr, thd vs r in for 0-5v single-ended input signal. r in () r1 () r2 () r3 () r4 () snr (db) thd (db) 2k 1k 1k 2k 665 92 C101 10k 5k 5k 10k 3.3k 91 C100 100k 50k 50k 100k 16k 91 C94 figure 7. lt6350 converting a 10v single-ended signal to a 2.5v differential input signal figure 7a. 32k point fft plot for circuit shown in figure 7 frequency (khz) 0 100 200 300 400 500 C180 amplitude (dbfs) C60 C40 C20C80 C100C120 C140 C160 0 238316 f06a snr = 92dbthd = C101db sinad = 91.4db sfdr = 103db frequency (khz) 0 100 200 300 400 500 C180 amplitude (dbfs) C60 C40 C20C80 C100C120 C140 C160 0 238316 f07a snr = 92dbthd = C97db sinad = 91.2db sfdr = 99.7db downloaded from: http:///
ltc2383-16 13 238316fa for more information www.linear.com/ltc2383-16 applications information table 2. snr, thd vs r in for 10v single-ended input signal. r in () r1 () r2 () r3 () r4 () snr (db) thd (db) 10k 1.24k 1.24k 10k 1.1k 92 C96 50k 6.19k 6.19k 50k 5.49k 91 C96 100k 12.4k 12.4k 100k 11k 91 C96 adc reference the ltc2383 -16 requires an external reference to define its input range. a low noise, low temperature drift reference is critical to achieving the full data sheet performance of the adc. linear technology offers a portfolio of high performance references designed to meet the needs of many applications. with its small size, low power and high accuracy, the ltc6652 -2.5 is particularly well suited for use with the ltc2383 -16. the ltc6652 -2.5 offers 0.05% (max) initial accuracy and 5ppm / c (max) temperature co - efficient for high precision applications. the ltc6652-2.5 is fully specified over the h-grade temperature range and complements the extended temperature operation of the ltc2383 -16 up to 125c . we recommend bypassing the ltc6652 -2.5 with a 47f ceramic capacitor (x5r, 0805 size) close to the ref pin. all performance curves shown in this data sheet were obtained using the ltc6652-2.5. the ref pin of the ltc2383 -16 draws charge (q conv ) from the 47f bypass capacitor during each conversion cycle. the reference replenishes this charge with a dc current, i ref = q conv /t cyc . the dc current draw of the ref pin, i ref , depends on the sampling rate and output code. if the ltc2383 -16 is used to continuously sample a signal at a constant rate, the ltc6652 -2.5 will keep the deviation of the reference voltage over the entire code span to less than 0.5lsbs. when idling, the ref pin on the ltc2383 -16 draws only a small leakage current ( < 1a ). in applications where a burst of samples is taken after idling for long periods as shown in figure 8, i ref quickly goes from approximately 0a to a maximum of 910a at 1msps . this step in dc current draw triggers a transient response in the reference that must be considered since any deviation in the reference output voltage will affect the accuracy of the output code. in applications where the transient response of the refer - ence is important, the fast settling ltc6655 -2.5 reference is recommended. inserting a 1 resistor between the 47f bypass capacitor and reference output as shown in figure 9 helps to improve the transient settling time and minimize the reference voltage deviation. cnv idle period idle period 238316 f08 figure 8. cnv waveform showing burst sampling 238316 f09 ltc2383-16 1 47f ltc6655-2.5 v out_s v out_f figure 9. ltc6655-2.5 driving ref of ltc2381-16 dynamic performance fast fourier transform (fft) techniques are used to test the adc s frequency response, distortion and noise at the rated throughput. by applying a low distortion sine wave and analyzing the digital output using an fft algorithm, the adc s spectral content can be examined for frequen - cies outside the fundamental. the ltc2383 -16 provides guaranteed tested limits for both ac distortion and noise measurements. downloaded from: http:///
ltc2383-16 14 238316fa for more information www.linear.com/ltc2383-16 figure 10. 32k point fft of the ltc2383-16 frequency (khz) 0 100 200 300 400 500 C180 amplitude (dbfs) C60 C40 C20C80 C100C120 C140 C160 0 238316 f10 snr = 92.2dbthd = C106.2db sinad = 92db sfdr = 110.4db applications information signal-to-noise and distortion ratio (sinad)the signal-to-noise and distortion ratio (sinad) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components at the a/d output. the output is band-limited to frequencies from above dc and below half the sampling frequency. figure 10 shows that the ltc2383 -16 achieves a typical sinad of 92db at a 1mhz sampling rate with a 20khz input.signal-to-noise ratio (snr) the signal-to-noise ratio (snr) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components except the first five harmonics and dc. figure 10 shows that the ltc2383 -16 achieves a typical snr of 92db at a 1mhz sampling rate with a 20khz input. total harmonic distortion (thd) total harmonic distortion (thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency (f sm- pl /2). thd is expressed as: thd vvv v v n = ++ ++ 20 23 4 1 22 22 lo g where v1 is the rms amplitude of the fundamental fre- quency and v2 through v n are the amplitudes of the second through nth harmonics. power considerations the ltc2383 -16 provides two power supply pins : the 2.5v power supply (v dd ), and the digital input/output interface power supply (ov dd ). the flexible ov dd supply allows the ltc2383 -16 to communicate with any digital logic operating between 1.8v and 5v , including 2.5v and 3.3v systems.power supply sequencing the ltc2383 -16 does not have any specific power supply sequencing requirements. care should be taken to adhere to the maximum voltage relationships described in the absolute maximum ratings section. the ltc2383-16 has a power-on-reset (por) circuit that will reset the ltc2383 -16 at initial power-up or whenever the power supply voltage drops below 1v . once the supply voltage reenters the nominal supply voltage range, the por will reinitialize the adc. no conversions should be initiated until 20s after a por event to ensure the reinitialization period has ended. any conversions initiated before this time will produce invalid results. timing and control cnv timing the ltc2383 -16 conversion is controlled by cnv. a rising edge on cnv will start a conversion. once a conversion has been initiated, it cannot be restarted until the conver - sion is complete. for optimum performance, cnv should be driven by a clean low jitter signal. converter status is indicated by the busy output which remains high while the conversion is in progress. to ensure that no errors occur in the digitized results, any additional transitions on cnv should occur within 40ns from the start of the conversion or after the conversion has been completed. once the conversion has completed, the ltc2383-16 begins acquiring the input signal. downloaded from: http:///
ltc2383-16 15 238316fa for more information www.linear.com/ltc2383-16 internal conversion clock the ltc2383 -16 has an internal clock that is trimmed to achieve a maximum conversion time of 730ns . with a min- imum acquisition time of 250ns , throughput performance of 1msps is guaranteed without any external adjustments. auto power-down the ltc2383 -16 automatically powers down after a con - version has been completed as long as cnv remains high. during power down, the data from the last conversion can be clocked out. to minimize power dissipation during power down, disable sdo and turn off sck. to power up the part, bring cnv low at least 200ns (t convl ) before the initiation of the next conversion. the auto power-down feature will reduce the power dissipation of the ltc2383 -16 as the sampling frequency is reduced. since the time required to power up the part does not change at lower sample rates, the ltc2383 -16 can remain powered-down for a larger fraction of the conversion cycle (t cyc ), thereby reducing the average power dissipation which scales linearly with sampling rate as shown in figure 11. applications information digital interface the ltc2383 -16 has a serial digital interface. the flexible ov dd supply allows the ltc2383 -16 to communicate with any digital logic operating between 1.8v and 5v , including 2.5v and 3.3v systems.the serial output data is clocked out on the sdo pin when an external clock is applied to the sck pin if sdo is enabled. clocking out the data after the conversion will yield the best performance. with a shift clock frequency of at least 60mhz , a 1msps throughput is still achieved. the serial output data changes state on the rising edge of sck and can be captured on the falling edge or next rising edge of sck. d15 remains valid till the first rising edge of sck. the serial interface on the ltc2383 -16 is simple and straightforward to use. the following sections describe the operation of the ltc2383 -16. several modes are provided depending on whether a single or multiple adcs share the spi bus or are daisy-chained. sampling rate (khz) 0 200 400 600 800 1000 0 power supply current (ma) 54 2 1 3 6 238316 f11 figure 11. power supply current of the ltc2383-16 versus sampling rate downloaded from: http:///
ltc2383-16 16 238316fa for more information www.linear.com/ltc2383-16 normal mode, single devicewhen chain = 0, the ltc2383 -16 operates in normal mode. in normal mode, rdl/sdi enables or disables the serial data output pin sdo. if rdl/sdi is high, sdo is in high-impedance. if rdl/sdi is low, sdo is driven. figure 12 shows a single ltc2383 -16 operated in normal mode with chain and rdl/sdi tied to ground. with rdl/sdi grounded, sdo is enabled and the msb( d15 ) of the new conversion data is available at the falling edge of busy. this is the simplest way to operate the ltc2383-16. cnv ltc2383-16 busy convert irq data in digital host clk sdo sck 238316 f12a rdl/sdi chain 238316 f12 convert convert power-down power-up t acq t acq = t cyc C t conv C t busylh acquire acquire cnv chain = 0 busy sck sdo (rdl/sdi = 0) t busylh t dsdobusyl t sck t hsdo t sckh t sckl t dsdo t conv t cnvh t cyc t cnvl d15 d14 d13 d1 d0 1 2 3 14 15 16 figure 12. using a single ltc2383-16 in normal mode applications information downloaded from: http:///
ltc2383-16 17 238316fa for more information www.linear.com/ltc2383-16 normal mode, multiple devicesfigure 13 shows multiple ltc2383 -16 devices operating in normal mode(chain = 0) sharing cnv, sck and sdo. by sharing cnv, sck and sdo, the number of required signals to operate multiple adcs in parallel is reduced. since sdo is shared, the rdl/sdi input of each adc must be used to allow only one ltc2383 -16 to drive sdo at a time in order to avoid bus conflicts. as shown in figure 13, the rdl/sdi inputs idle high and are individually brought low to read data out of each device between conversions. when rdl/sdi is brought low, the msb of the selected device is output onto sdo. to ensure the msb is properly output and captured, sck must be held low at least 1ns before and 16ns after bringing rdl/sdi low. 238316 f13 rdl2rdl1 convert irq data in digital host clk cnv ltc2383-16 sdo a sck rdl/sdi cnv ltc2383-16 sdo b sck rdl/sdi chain busy chain 238316 f13 d15 a sdo sck cnv busy chain = 0 rdl/sdi b rdl/sdi a d15 b d14 b d1 b d0 b d13 b d14 a d13 a d1 a d0 a hi-z hi-z hi-z t en t hsdo t dsdo t dis t sckl t sckh t cnvl 1 2 3 14 15 16 17 18 19 30 31 32 t sck power-up convert power-down convert acquire acquire t hsckrdl t ssckrdl t conv t busylh figure 13. normal mode with multiple devices sharing cnv, sck and sdo applications information downloaded from: http:///
ltc2383-16 18 238316fa for more information www.linear.com/ltc2383-16 ov dd 238316 f14a convert irq data in digital host clk cnv ltc2383-16 busy sdo b sck rdl/sdi cnv ltc2383-16 sdo a sck rdl/sdi chain ov dd chain when chain = ov dd , the ltc2383 -16 operates in chain mode. in chain mode, sdo is always enabled and rdl/ sdi serves as the serial data input pin (sdi) where daisy chain data output from another adc can be input. this is useful for applications where hardware constraints may limit the number of lines needed to interface to a large number of converters. figure 14 shows an example with two daisy chained devices. the msb of converter a will appear at sdo of converter b after 16 sck cycles. the msb of converter a is clocked in at the sdi/rdl pin of converter b on the rising edge of the first sck. 238316 f14 d0 a d1 a d14 a d15 a d13 b d14 b d15 b sdo b sdo a = rdl/sdi b rdl/sdi a = 0 d0 b d1 b d13 a d14 a d15 a d0 a d1 a 1 2 3 14 15 16 17 18 30 31 32 t dsdobusyl t ssdisck t hsdisck t busylh t conv t hsdo t dsdo t sckl t sckh t sckch t cnvl t cyc convert convert acquire acquire power-down power-up sck cnv busy chain = ov dd figure 14. chain mode timing diagram applications information downloaded from: http:///
ltc2383-16 19 238316fa for more information www.linear.com/ltc2383-16 board layout to obtain the best performance from the ltc2383-16 a printed circuit board is recommended. layout for the printed circuit board (pcb) should ensure the digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital clocks or signals alongside analog signals or underneath the adc. recommended layout the following is an example of a recommended pcb layout. a single solid ground plane is used. bypass capacitors to the supplies are placed as close as possible to the supply pins. low impedance common returns for these bypass capacitors are essential to the low noise operation of the adc. the analog input traces are screened by ground. for more details and information refer to dc1571 a, the evaluation kit for the ltc2383-16. 238316 bl01 partial top silkscreen downloaded from: http:///
ltc2383-16 20 238316fa for more information www.linear.com/ltc2383-16 board layout partial layer 1 component side 238316 bl03 partial layer 2 ground plane 238316 bl02 downloaded from: http:///
ltc2383-16 21 238316fa for more information www.linear.com/ltc2383-16 board layout partial layer 3 pwr plane 238316 bl04 238316 bl05 partial layer 4 bottom layer downloaded from: http:///
ltc2383-16 22 238316fa for more information www.linear.com/ltc2383-16 u6 nc7sz66p5x c13 0.1f 4 1 2 9 cnv sck c2047f 6.3v 0805 c56 0.1f cnv ref gndgnd gnd gnd ref1 v dd v ref 0.8v ref ov dd sck sdo busy rdl/sdi sdobusy rd ltc2383-16 in C in + 1314 11 12 b a 5 3 gnd v cc oe +3.3v jp4 ref ext6652 hd1x3-100 r549.9 1206 r61k u8nc7sz04p5x u2nc7svu04p5x u10 ltc6652ahms8-2.5 u3 nl17sz74 u4nc7svu04p5x cnvst_33from cpld clkto cpld c5 0.1f c1 0.1f c11 0.1f dncgnd gndgnd gnd shdn 9v to 10v 1 23 4 8 32 1 76 5 +3.3v +3.3v +3.3v 3 4 2 5 3 4 2 5 c2 0.1f r3 33 r21k r1 33 +3.3v +3.3v 3 1 46 2 87 5 r833 c3 0.1f r4 33 c4 0.1f c12 1f e6 ext_ref v in v out gnd v cc clr\ q\ cp q d pr\ 3 4 2 5 +3.3v dc590 detectto cpld +3.3v c58 opt u9nc7sz04p5x c15 0.1f c16 0.1f 3 4 2 5 +3.3v r13 1k r172k r104.99k u724lc025-i/st r114.99k r124.99k c14 0.1f 6 84 57 3 2 1 sclsda array eeprom wpa2 a1 a0 v ss v cc 13 5 7 9 1113 24 6 8 10 12 14 j3 dc590 sdo sck cnv 9v to10v r71k 1016 6 31 15 7 28 jp6 fs 12 3 hd1x3-100 opt r1 ? c7 0.1f c610f 6.3v +2.5v c10 0.1f c39 opt npo c193300pf 1206 npo r38 opt r36 49.9 r35 opt r45? r34? c10 opt c910f 6.3v r1 100 r32 49.9 out1 v + v C v+ shdn out2 5 4 Cin1 +in1 8 7 3 +in2 2 6 r1 100 +C r18 1k r31 opt u15 lt6350cms8 r32 ? c4215pf c4510f c55 1f v + v C c57 0.1f r371k r91k c6110f 6.3v c63 10f 6.3v c6210f c43 1f r151k c18 opt c1710f jp2 cm e7 ext_cm 1 +2.5v 23 v ref/2 ext hd1x3-100 c8 1f c46 1f r401k r39 ? 12 3 couplingac dc jp1 hd1x3-100 c44 1f c49 opt c4810f 6.3v c47 opt r41 opt c59 1f c60 1f 12 3 jp5 hd1x3-100 couplingac dc db16 db17 3937 35 33 31 29 27 25 23 21 19 17 15 13 11 97 5 3 1 db0db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 clkout 1 4038 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 j2 con-edge 40-100 clk in r14 ? a in + a in ? C+ board layout partial schematic of demoboard downloaded from: http:///
ltc2383-16 23 238316fa for more information www.linear.com/ltc2383-16 package description 3.00 0.10 (2 sides) 4.00 0.10 (2 sides) note:1. drawing proposed to be made variation of version (wged-3) in jedec package outline mo-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom viewexposed pad 1.70 0.10 0.75 0.05 r = 0.115 typ r = 0.05 typ 3.15 ref 1.70 0.05 1 8 16 9 pin 1 top mark (see note 6) 0.200 ref 0.00 C 0.05 (de16) dfn 0806 rev ? pin 1 notchr = 0.20 or 0.35 45 chamfer 3.15 ref recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 2.20 0.05 0.70 0.05 3.60 0.05 packageoutline 0.25 0.05 3.30 0.05 3.30 0.10 0.45 bsc 0.23 0.05 0.45 bsc de package 16-lead plastic dfn (4mm 3mm) (reference ltc dwg # 05-08-1732 rev ?) please refer to http://www.linear.com/product/ltc2383-16#packaging for the most recent package drawings. downloaded from: http:///
ltc2383-16 24 238316fa for more information www.linear.com/ltc2383-16 msop (ms16) 0213 rev a 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 C?0.27 (.007 C .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 16151413121110 1 2 3 4 5 6 7 8 9 note:1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 C 6 typ detail a detail a gauge plane 5.10 (.201) min 3.20 C 3.45 (.126 C .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc 4.039 0.102 (.159 .004) (note 3) 0.1016 0.0508 (.004 .002) 3.00 0.102 (.118 .004) (note 4) 0.280 0.076 (.011 .003) ref 4.90 0.152 (.193 .006) ms package 16-lead plastic msop (reference ltc dwg # 05-08-1669 rev a) package description please refer to http://www.linear.com/product/ltc2383-16#packaging for the most recent package drawings. downloaded from: http:///
ltc2383-16 25 238316fa for more information www.linear.com/ltc2383-16 revision history rev date description page number a 07/16 updated graphs g01, g02 and g03 6 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. downloaded from: http:///
ltc2383-16 26 238316fa ? linear technology corporation 2010 lt 0716 rev a ? printed in usa for more information www.linear.com/ltc2383-16 related parts typical application part number description comments adcs ltc2393-16 16-bit, 1msps parallel/serial adc 5v supply, differential input, 94db snr, 4.096v input range, 48-pin lqfp package, pin compatible with the ltc2392-16, ltc2391-16 ltc2392-16 16-bit, 500ksps parallel/serial adc 5v supply, differential input, 94db snr, 4.096v input range, 48-pin lqfp package, pin compatible with the ltc2393-16, ltc2391-16 ltc2391-16 16-bit, 250ksps parallel/serial adc 5v supply, differential input, 94db snr, 4.096v input range, 48-pin lqfp package, pin compatible with the ltc2393-16, ltc2392-16 ltc1864/ltc1864l 16-bit, 250ksps/150ksps 1-channel power adc 5v/3v supply, 1-channel, 4.3mw/1.3mw, msop-8 package ltc1865/ltc1865l 16-bit, 250ksps/150ksps 2-channel power adc 5v/3v supply, 2-channel, 4.3mw/1.3mw, msop-8 package ltc2302/ltc2306 12-bit, 500ksps, 1-/2-channel, low noise, adc 5v supply, 14mw at 500ksps, 10-pin dfn package ltc2355-14 / ltc2356-14 14-bit, 3.5msps serial adc 3.3v supply, 1-channel, unipolar/bipolar, 18mw, msop-10 package dacs ltc2641 16-bit single serial v out dacs 1lsb inl, 1lsb dnl, msop-8 package, 0v to 5v output ltc2630 12-/10-/8-bit single v out dacs sc70 6-pin package, internal reference, 1lsb inl (12 bits) references ltc6652 precision low drift low noise buffered reference 2.5v, 5ppm/c max tempco, 2.1ppm peak-to-peak noise, msop-8 package ltc6655 precision low drift low noise buffered reference 2.5v, 5ppm / c max tempco, 0.25ppm peak-to-peak noise, msop-8 package amplifiers lt6350 low noise single-ended-to-differential adc driver rail-to-rail input and outputs, 240ns 0.01% settling time, dfn-8 or msop-8 packages lt6200/lt6200-5/lt6200-10 165mhz/800mhz/1.6ghz op amp with unity gain/av = 5/av = 10 low noise voltage: 0.95nv/ hz (100khz), low distortion: C80db at 1mhz, tsot23-6 package lt6202/lt6203 single/dual 100mhz rail-to-rail input/output noise low power amplifiers 1.9nv hz , 3ma maximum, 100mhz gain bandwidth ltc1992 low power, fully differential input/output amplifier/driver family 1ma supply current 50 3300pf 6600pf 50 500 100100 lpf2 lpf1 bw = 482khz bw = 48khz single-ended input signal ltc2383-16 in + in C 238316 ta03 lt6350 v cm = v ref /2 r int r int 8 4 5 2 1 + C +C +C frequency (khz) 0 100 200 300 400 500 C180 amplitude (dbfs) C60 C40 C20C80 C100C120 C140 C160 0 238316 ta04 snr = 92.2dbthd = C106.2db sinad = 92db sfdr = 110.4db adc driver: single-ended input to differential output with filter linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc2383-16 downloaded from: http:///

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